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| 1/9/98 11:56 am 24346802.doc intel confidential (until publication date) january 1998 order number: 243468-002 operating frequency 166 mhz 200 mhz 233 mhz 266 mhz n support for mmx? technology n compatible with large software base ? ms-dos*, windows*, os/2*, unix* n 32-bit cpu with 64-bit data bus n superscalar architecture ? enhanced pipelines ? two pipelined integer units capable of 2 instructions/clock ? pipelined mmx technology ? pipelined floating-point unit n separate code and data caches ? 16-kbyte code, 16-kbyte write back data ? mesi cache protocol n 4-mbyte pages for increased tlb hit rate n 320-pin tcp or mobile module n ieee 1149.1 boundary scan n advanced design features ? deeper write buffers ? enhanced branch prediction feature ? virtual mode extensions n 0.25 micron process technology ? 1.8 v core supply (166/200/233 mhz) ? 2.0 v core supply (266 mhz) ? 2.5 v i/o interface (166/200/233/266 mhz ) n internal error detection features n on-chip local apic controller n power management features ? system management mode ? clock control n fractional bus operation ? 166-mhz core/66-mhz bus ? 200-mhz core/66-mhz bus ? 233-mhz core/66-mhz bus ? 266-mhz core/66-mhz bus the mobile pentium ? processor with mmx? technology on 0.25 micron extends the mobile pentium processor family, providing additional performance for notebook applications. the mobile pentium processor with mmx technology on 0.25 micron is compatible with the entire installed base of applications for ms- dos*, windows*, os/2*, and unix* and is one of the major microprocessors to support intel mmx technology. furthermore, the mobile pentium processor with mmx technology on 0.25 micron has superscalar architecture which can execute two instructions per clock cycle, and enhanced branch prediction and separate caches also increase performance. the pipelined floating-point unit delivers workstation level performance. separate code and data caches reduce cache conflicts while remaining software transparent. the mobile pentium processor with mmx technology on 0.25 micron has 4.5 million transistors, is built on intel's 0.25 micron manufacturing process technology and has full sl enhanced power management features including system management mode (smm) and clock control. the additional sl enhanced features, 1.8/2.0v core operation along with 2.5v i/o buffer operation, a 320-pin tape carrier package (tcp), and the intel mobile module, make the mobile pentium processor with mmx technology on 0.25 micron ideal for enabling mobile mmx technology designs. the mobile pentium processor with mmx technology on 0.25 micron may contain design defects or errors known as errata which may cause the product to deviate from published specifications. current characterized errata are available upon request. mobile pentium? processor with mmx? technology on 0.25 micron
mobile pentium ? processor with mmx? technology 2 1/9/98 11:56 am 24346802.doc intel confidential (until publication date) information in this document is provided in connection with intel products. no license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted by this document. except as provided in intel?s terms and conditions of sale for such products, intel assumes no liability whatsoever, and intel disclaims any express or implied warranty, relating to sale and/or use of intel products including liability or warranties relating to fitness for a particular purpose, merchantability, or infringement of any patent, copyright or other intellectual property right. intel products are not intended for use in medical, life saving, or life sustaining applications. designers must not rely on the absence or characteristics of any features or instructions marked "reserved" or "undefined." intel reserves these for future definition and shall have no responsibility whatsoever for conflicts or incompatibilities arising from future changes to them. intel may make changes to specifications and product descriptions at any time, without notice. the mobile pentium? processor with mmx ? technology may contain design defects or errors known as errata which may cause the product to deviate from published specifications. current characterized errata are available on request. mpeg is an international standard for video compression/decompression promoted by iso. implementations of mpeg codecs, or mpeg enabled platforms may require licenses from various entities, including intel corporation. contact your local intel sales office or your distributor to obtain the latest specifications and before placing your product order. copies of documents which have an ordering number and are referenced in this document, or other intel literature, may be obtained by calling 1-800-548-4725 or by visiting intel?s website at http://www.intel.com copyright ? intel corporation1997. third-party brands and names are the property of their respective owners. mobile pentium ? processor with mmx? technology 3 1/9/98 12:41 pm 24346802.doc intel confidential (until publication date) contents page page 1.0. introduction ................................ ............ 4 2.0. microprocessor architecture overview ................................ .................... 4 2.1. mobile pentium ? processor family architecture ................................ ................ 5 2.2. mobile pentium ? processor with mmx tm technology ................................ ................. 7 2.2.1. full support for intel mmx tm technology ................................ ........... 7 2.2.2. doubled code and data caches to 16k each ................................ ..................... 7 2.2.3. improved branch prediction .................. 7 2.2.4. enhanced pipeline ................................ 8 2.3 0.25 micron technology.???????..8 3.0. mobile pentium ? processor with mmx? technology pinout ................... 8 3.1. mobile differences from desktop ................ 8 3.2. tcp pinout and pin descriptions ................ 9 3.2.1. tcp mobile pentium ? processor with mmx? technology pinout ..................... 9 3.2.2. tcp mobile pentium ? processor with mmx? technology pin cross reference ................................ ..... 10 3.3. design notes ................................ ............ 17 3.4. quick pin reference ................................ . 17 3.5. bus frequency ................................ ......... 26 3.6. pin reference tables ............................... 27 3.7. pin grouping according to function .......... 30 4.0. electrical specifications ................ 31 4.1. maximum ratings ................................ ..... 31 4.2. dc specifications ................................ ...... 31 4.2.1. power sequencing ..................... 31 4.3. ac specifications ................................ ...... 34 4.3.1. power and ground .................... 34 4.3.2. decoupling recommendation 34 4.3.3. connection specifications ..... 35 4.3.4. ac timings for a 66-mhz bus .... 35 4.4. i/o buffer models ................................ ...... 46 4.4.1. buffer model parameters ...... 49 4.4.2. signal quality specification .. 51 4.4.3. clock signal measurement methodology ............................... 55 5.0. mechanical specifications ............... 57 5.1. tcp mechanical diagrams ....................... 58 6.0. thermal specifications ..................... 64 6.1. measuring thermal values for tcp .......... 64 6.1.1. tcp thermal equations ..................... 64 6.1.2. tcp thermal characteristics ............. 64 6.1.3. tcp pc board enhancements ........... 64 6.1.3.1. tcp standard test board configuration ............................. 65 mobile pentium ? processor with mmx? technology 4 1/9/98 11:56 am 24346802.doc intel confidential (until publication date) 1. 0. introduction the mobile pentium? processors with mmx? technology on 0.25 micron are fully compatible with the existing mobile pentium processors with mmx technology ( 120 , 133, 150, & 166 mhz) with the following differences: voltage supplies, power consumption, and performance. these processors, when used in a tcp package, are socket compatible with the mobile pentium processor (75, 90, 100, 120, 133, 150 mhz) making it possible to design a flexible motherboard that supports both the mobile pentium processor (75 mhz - 150 mhz) and the mobile pentium processor with mmx technology ( 120 mhz - 266 mhz). it has all the advanced features of the desktop version of the pentium processor with mmx technology except for the differences listed in section 3.1. the mobile pentium processor with mmx technology on 0.25 micron has several features which allow high-performance notebooks to be designed, including the following: tcp dimensions are ideal for small form-factor designs. tcp has superior thermal resistance characteristics. 1.8v (166/200/233 mhz)/2.0v (266 mhz) core and 2.5v i/o buffer v cc inputs reduce power consumption significantly. the sl enhanced feature set. the architecture and internal features of the mobile pentium processor with mmx technology on 0.25 micron are identical to the desktop version specifications provided in the pentium ? processor family developer?s manual (order number 241428 ) , except several features not used in mobile applications which have been eliminated to streamline it for mobile applications. this document should be used in conjunction with pentium ? processor family developer?s manual (order number: 241428) 2. 0. microprocessor architecture overview the mobile pentium processor with mmx technology on 0.25 micron extends the mobile pentium processor with mmx technology family. it is binary compatible with the 8086/88?, 80286?, intel386? dx, intel386 sx, intel486? dx, intel486 sx, intel486 dx2, and mobile pentium processors with voltage reduction technology (75- 150). the mobile pentium processor family consists of the mobile pentium processor with mmx technology ( 120, 133, 150, & 166 ), the mobile pentium processor with mmx technology on 0.25 micron (166, 200, 233, & 266) and the mobile pentium processor with voltage reduction technology (75 mhz -150 mhz). the mobile pentium processor with mmx technology on 0.25 micron contains all of the features of previous intel architecture and provides significant en hancements and additions including the following: support for mmx? technology superscalar architecture enhanced branch prediction algorithm pipelined floating-point unit improved instruction execution time separate 16k code and 16k data caches writeback mesi protocol in the data cache 64-bit data bus enhanced bus cycle pipelining address parity internal parity checking execution tracing performance monitoring ieee 1149.1 boundary scan system management mode virtual mode extensions 0.25 micron process technology sl power management features pool of four write buffers used by both pipes mobile pentium ? processor with mmx? technology 5 1/9/98 11:56 am 24346802.doc intel confidential (until publication date) 2.1. mobile pentium ? processor family architecture the application instruction set of the mobile pentium processor family includes the complete intel486 cpu family instruction set with extensions to accommodate some of the additional functionality of the pentium processors. all application software written for the intel386 and intel486 family microprocessors will run on the pentium processors without modification. the on- chip memory management unit (mmu) is completely compatible with the intel386 and intel486 families of processors. the pentium processors implement several enhancements to increase performance. the two instruction pipelines and floating-point unit on pentium processors are capable of independent operation. each pipeline issues frequently used instructions in a single clock. together, the dual pipes can issue two integer instructions in one clock, or one floating-point instruction (under certain circumstances, two floating-point instructions) in one clock. branch prediction is implemented in the pentium processors. to support this, pentium processors implement two prefetch buffers, one to prefetch code in a linear fashion, and one that prefetches code according to the branch target buffer (btb) so the needed code is almost always prefetched before it is needed for execution. the floating-point unit has been completely redesigned over the intel486 processor. faster algorithms provide up to 10x speed-up for common operations including add, multiply and load. pentium processors include separate code and data caches integrated on-chip to meet performance goals. each cache has a 32-byte line size and is 4-way set associative. each cache has a dedicated translation lookaside buffer (tlb) to translate linear addresses to physical addresses. the data cache is configurable to be writeback or writethrough on a line-by-line basis and follows the mesi protocol. the data cache tags are triple ported to support two data transfers and an inquire cycle in the same clock. the code cache is an inherently write-protected cache. the code cache tags are also triple ported to support snooping and split line accesses. individual pages can be configured as cacheable or non-cacheable by software or hardware. the caches can be enabled or disabled by software or hardware. the pentium processors have increased the data bus to 64 bits to improve the data transfer rate. burst read and burst writeback cycles are supported by the pentium processors. in addition, bus cycle pipelining has been added to allow two bus cycles to be in progress simultaneously. the pentium processors' mmu contains optional extensions to the architecture which allow 4-kbyte and 4-mbyte page sizes. the pentium processors have added significant data integrity and error detection capability. data parity checking is still supported on a byte-by-byte basis. address parity checking and internal parity checking features have been added along with a new exception, the machine check exception. as more and more functions are integrated on chip, the complexity of board level testing is increased. to address this, the pentium processors have increased test and debug capability. the pentium processors implement ieee boundary scan (standard 1149.1). in addition, the pentium processors have specified four breakpoint pins that correspond to each of the debug registers and externally indicate a breakpoint match. execution tracing provides external indications when an instruction has completed execution in either of the two internal pipelines, or when a branch has been taken. system management mode (smm) has been implemented along with some extensions to the smm architecture. enhancements to the virtual 8086 mode have been made to increase performance by reducing the number of times it is necessary to trap to a vir tual 8086 monitor. figure 1 shows a block diagram of the mobile pentium processor with mmx technology. the block diagram shows the two instruction pipelines, the "u" pipe and "v" pipe. the u-pipe can execute all integer and floating-point instructions. the v-pipe can exe cute simple integer instructions and the fxch floating-point instructions. mobile pentium ? processor with mmx? technology 6 1/9/98 11:56 am 24346802.doc intel confidential (until publication date) the separate code and data caches are shown,. the data cache has two ports, one for each of the two pipes (the tags are triple ported to allow simultaneous inquire cycles). the data cache has a dedicated translation lookaside buffer (tlb) to translate linear addresses to the physical addresses used by the data cache. branch target buffer code cache 16 kbytes rom control unit generate address generate data cache 16 kbytes 128 tlb tlb prefetch address prefetch buffers instruction decode i nstruction pointer integer register file alu barrel shifter 32 32 32 32 32 32 page unit bus unit 32-bit address bus control 64-bit data bus 32-bit addr. bus 64 control register file add multiply divide floating- point unit control 80 80 address (u pipeline) (v pipeline) (u pipeline) (v pipeline) alu pp0115 branch verif. & target addr 32 64-bit data bus mmx tm unit v-pipeline connection u-pipeline connection data control apic figure 1 . mobile pentium ? processor with mmx? technology block diagram mobile pentium ? processor with mmx? technology 7 1/9/98 11:56 am 24346802.doc intel confidential (until publication date) the code cache, branch target buffer and prefetch buffers are responsible for getting raw instructions into the execution units of the mobile pentium processor. instructions are fetched from the code cache or from the external bus. branch addresses are remembered by the branch target buffer. the code cache tlb translates linear addresses to physical addresses used by the code cache. the decode unit decodes the prefetched instructions so the mobile pentium processor can execute the instruction. the control rom contains the microcode which controls the sequence of operations that must be performed to implement the mobile pentium processor architecture. the control rom unit has direct control over both pipelines. the mobile pentium processor contains a pipelined floating-point unit that provides a significant floating-point performance advantage over previous generations of processors. in addition to the smm features described above, the mobile pentium processor supports clock control. when the clock to the processor is stopped, power dissipation is virtually eliminated. the combination of these improvements makes the mobile pentium processor a good choice for energy-efficient notebook designs. the mobile pentium processor supports fractional bus operation. this allows the internal processor core to operate at high frequencies, while communicating with the external bus at lower frequencies. the mobile pentium ? processor with mmx? technology on 0.25 micron contains an on-chip advanced programmable interrupt controller (apic). this function is reserved for future multi-processing function. the architectural features introduced in this section are more fully described in the pentium ? processor family developer's manual (order number: 241428). 2.2. mobile pentium ? processor with mmx tm technology the mobile pentium processor with mmx technology is a significant addition to the mobile pentium processor family. available at 120, 133, 150, 166, 200, 233, and 266 mhz , it is the first microprocessor to support intel mmx technology. the mobile pentium processor with mmx technology is both software and pin compatible with previous members of the mobile pentium processor family. it contains 4.5 million transistors and is manufactured on lntel's enhanced 0.35 micron ( 120 /133/150/166 mhz) or 0.25 micron ( 166 /200/233/ 266 mhz) cmos process which allows voltage reduction technology for low power and high density. this enables the mobile pentium processor with mmx technology to remain within the thermal envelope while providing a significant performance increase. in addition to the architecture described in the previous section for the mobile pentium processor family, the mobile pentium processor with mmx technology has several additional micro- architectural enhancements, which are described below. 2.2.1. full support for intel mmx tm technology mmx technology is based on simd technique (single instruction, multiple data) which enables increased performance on a wide variety of multimedia and communications applications. fifty- seven new instructions and four new 64-bit data types are supported in the mobile pentium processor with mmx technology. all existing operating system and application software are fully- compatible. 2.2.2. doubled code / data caches to 16k each on-chip level-1 data and code cache sizes have been doubled to 16kb each and are 4-way set associative on the mobile pentium processor with mmx technology. larger separate internal caches improve performance by reducing average memory access time and providing fast access to recently- used instructions and data. the instruction and data caches can be accessed simultaneously while the data cache supports two data references simultaneously. the data cache supports a write- back (or alternatively, write-through, on a line by line basis) policy for memory updates. 2.2.3. improved branch prediction dynamic branch prediction uses the branch target buffer (btb) to boost performance by predicting the most likely set of instructions to be executed. the btb has been improved on the mobile pentium processor with mmx technology to increase its accuracy. further, this processor has four prefetch mobile pentium ? processor with mmx? technology 8 1/9/98 11:56 am 24346802.doc intel confidential (until publication date) buffers that can hold up to four successive code streams. 2.2.4. enhanced pipeline an additional pipeline stage has been added and the pipeline has been enhanced to improve performance. the integration of the mmx technology pipeline with the integer pipeline is very similar to that of the floating-point pipeline. under some circumstances, two mmx instructions or one integer and one mmx instruction can be paired and issued in one clock cycle to increase throughput. the enhanced pipeline is described in more detail in the pentium ? processor family developer?s manual (order number 241428). deeper write buffers. a pool of four write buffers is now shared between the dual pipelines to improve memory write performance. 2.3. 0.25 micron technology the 0.25 micron technology is the latest state-of- the-art cmos manufacturing process intel unveiled on april 12, 1997, which enables the use of lower core supply to sub-2v. as a result, the mobile pentium processor with mmx technology on 0.25 micron consumes significantly less power at even higher speeds. the mobile pentium processor with mmx technology on 0.25 micron is the first intel microprocessor utilizing 0.25 micron technology. 3.0. mobile pentium ? processor with mmx? technology pinout 3.1. mobile differences from desktop to better streamline the part for mobile applications, the following features have been eliminated: upgrade, dual processing (dp), and master/checker functional redundancy. table 1 lists the corresponding pins which exist on the desktop pentium processor with mmx technology but have been removed on the mobile pentium processor with mmx technology on 0.25 micron. table 1 . signals removed in mobile pentium ? processor with mmx? technology 200/233 mhz signal function adsc# additional address status. this signal is mainly used for large or standalone l2 cache memory subsystem support required for high-performance desktop or server models. brdyc# additional burst ready. this signal is mainly used for large or standalone l2 cache memory subsystem support required for high-performance desktop or server models. cputyp cpu type. this signal is used for dual processing systems. d/p# dual/primary processor identification. this signal is only used for an upgrade processor. frcmc# functional redundancy checking. this signal is only used for error detection via processor redundancy and requires two pentium ? processors (master/checker). pbgnt# private bus grant. this signal is only used for dual processing systems. pbreq# private bus request. this signal is used only for dual processing systems. phit# private hit. this signal is only used for dual processing systems. phitm# private modified hit. this signal is only used for dual processing systems. mobile pentium ? processor with mmx? technology 9 1/9/98 11:56 am 24346802.doc intel confidential (until publication date) 3.2. tcp pinout and pin descriptions the text orientation on the top side view drawings in this section represent the orientation of the ink mark on the actual packages (note that the text shown in this section is not the actual text which will be marked on the packages). 3.2.1. mobile pentium ? processor with mmx? technology on 0.25 micron tcp pinout vcc2 240 239 238 237 236 235 234 233 232 231 230 vss a11 a10 vcc3 vss a9 vss vcc2 a8 vcc3 219 218 217 216 215 214 213 212 211 210 a3 vss vcc2 vcc3 vss a31 a30 a29 a28 vcc3 229 228 227 226 225 224 223 222 221 220 vss a7 a6 vcc3 vcc2 vss a5 a4 vcc3 vss 209 208 207 206 205 204 203 202 201 200 vss a27 a26 a25 a24 vcc3 vss a23 a22 a21 199 198 197 196 195 194 193 192 191 190 nmi r/s# intr smi# vcc2 vss ignne# init pen# vcc2 189 188 187 186 185 184 183 182 181 180 vss vcc2 vss bf0 bf1 bf2 vcc2 vss stpclk# vcc2 179 178 177 176 175 174 173 172 171 170 vss vcc3 vcc2 vss nc vcc2 vss vcc2 vss vcc2 169 168 167 166 165 164 163 162 161 vss vcc2 trst# vss vcc2 tms tdi tdo tck vcc2 1 2 3 4 5 6 7 8 9 10 11 vcc3 vss hold wb/wt# vcc2 na# boff# brdy# vcc2 22 23 24 25 26 27 28 29 30 31 m/io# vcc3 vss bp3 vss vcc2 bp2 pm1/bp1 pm0/bp0 ferr# 12 13 14 15 16 17 18 19 20 21 vss ken# ahold inv ewbe# vcc2 vss vcc3 vss cache# 32 33 34 35 36 37 38 39 40 41 vss vcc2 ierr# vcc3 vss dp7 d63 d62 d61 vcc2 42 43 44 45 46 47 48 49 50 51 vss vcc3 vss d60 d59 d58 d57 vcc2 vss vcc3 52 53 54 55 56 57 58 59 60 61 vss d56 dp6 d55 d54 vcc2 vss vcc3 vss d53 62 63 64 65 66 67 68 69 70 71 d52 d51 d50 vcc2 vss vcc3 vss d49 d48 dp5 72 73 74 75 76 77 78 79 80 d47 vcc3 vss d46 d45 d44 d43 vcc3 vss vss vss 320 319 318 317 316 315 314 313 312 311 310 smiact# prdy vcc2 pchk# apchk# vss vcc3 breq hlda vss 299 298 297 296 295 294 293 292 291 290 pwt d/c# eads# ads# vcc3 vss hitm# hit# vcc3 vss 309 308 307 306 305 304 303 302 301 300 vcc2 ap vss vcc3 vss vcc2 lock# vss vcc3 pcd 289 288 287 286 285 284 283 282 281 280 w/r# buschk# flush# a20m# be0# be1# be2# be3# vcc3 vss 279 278 277 276 275 274 273 272 271 270 be4# be5# be6# be7# vcc3 vss scyc clk nc reset 269 268 267 266 265 264 263 262 261 260 vss vcc2 vss vcc2 a20 vcc3 vss a19 vss vcc2 259 258 257 256 255 254 253 252 251 250 a18 vcc3 vcc2 vss a17 a16 vcc3 vss a15 vss 249 248 247 246 245 244 243 242 241 vcc2 a14 vcc3 vss a13 vss vcc2 a12 vcc3 d42 81 82 83 84 85 86 87 88 89 90 91 d41 d40 dp4 vcc3 vss d38 d37 d36 vcc3 102 103 104 105 106 107 108 109 110 111 d29 vcc3 vss d28 d27 d26 d25 vcc3 vss vcc2 92 93 94 95 96 97 98 99 100 101 vss d35 d34 d33 d32 vcc3 vss dp3 d31 d30 112 113 114 115 116 117 118 119 120 121 vss d24 dp2 d23 d22 vcc3 vss d21 d20 d19 122 123 124 125 126 127 128 129 130 131 d18 vcc3 vss d17 d16 dp1 d15 vcc3 vss d14 132 133 134 135 136 137 138 139 140 141 d13 d12 d11 vcc3 vss d10 d9 d8 dp0 vcc3 142 143 144 145 146 147 148 149 150 151 vss d7 d6 d5 d4 vcc3 vss d3 d2 d1 152 153 154 155 156 157 158 159 160 d0 vcc2 vss picclk picd0 vcc2 picd1 vss vcc3 d39 tcp pinout pp0116 figure 2 . tcp mobile pentium ? processor with mmx? technology on 0.25 micron pinout mobile pentium ? processor with mmx? technology 10 1/9/98 11:56 am 24346802.doc intel confidential (until publication date) 3.2.2. tcp mobile pentium ? processor with mmx? technology on 0.25 micron pin cross reference table 2 . tcp pin cross reference by pin name address a3 219 a9 234 a15 251 a21 200 a27 208 a4 222 a10 237 a16 254 a22 201 a28 211 a5 223 a11 238 a17 255 a23 202 a29 212 a6 227 a12 242 a18 259 a24 205 a30 213 a7 228 a13 245 a19 262 a25 206 a31 214 a8 231 a14 248 a20 265 a26 207 data d0 152 d13 132 d26 107 d39 87 d52 62 d1 151 d14 131 d27 106 d40 83 d53 61 d2 150 d15 128 d28 105 d41 82 d54 56 d3 149 d16 126 d29 102 d42 81 d55 55 d4 146 d17 125 d30 101 d43 78 d56 53 d5 145 d18 122 d31 100 d44 77 d57 48 d6 144 d19 121 d32 96 d45 76 d58 47 d7 143 d20 120 d33 95 d46 75 d59 46 d8 139 d21 119 d34 94 d47 72 d60 45 d9 138 d22 116 d35 93 d48 70 d61 40 d10 137 d23 115 d36 90 d49 69 d62 39 d11 134 d24 113 d37 89 d50 64 d63 38 d12 133 d25 108 d38 88 d51 63 apic picclk 155 picd0 156 picd1 158 mobile pentium ? processor with mmx? technology 11 1/9/98 11:56 am 24346802.doc intel confidential (until publication date) table 2. tcp pin cross reference by pin name (contd.) control a20m# 286 breq 312 hitm# 293 pm0/bp0 30 ads# 296 buschk# 288 hlda 311 pm1/bp1 29 ahold 14 cache# 21 hold 4 prdy 318 ap 308 d/c# 298 ierr# 34 pwt 299 apchk# 315 dp0 140 ignne# 193 r/s# 198 be0# 285 dp1 127 init 192 reset 270 be1# 284 dp2 114 intr/lint0 197 scyc 273 be2# 283 dp3 99 inv 15 smi# 196 be3# 282 dp4 84 ken# 13 smiact# 319 be4# 279 dp5 71 lock# 303 tck 161 be5# 278 dp6 54 m/io# 22 tdi 163 be6# 277 dp7 37 na# 8 tdo 162 be7# 276 eads# 297 nmi/lint1 199 tms 164 boff# 9 ewbe# 16 pcd 300 trst# 167 bp2 28 ferr# 31 pchk# 316 w/r# 289 bp3 25 flush# 287 pen# 191 wb/wt# 5 brdy# 10 hit# 292 clock control bf 0 186 bf1 185 bf2 184 clk 272 picclk 155 stpclk# 181 mobile pentium ? processor with mmx? technology 12 1/9/98 11:56 am 24346802.doc intel confidential (until publication date) table 2. tcp pin cross reference by pin name (contd.) v cc2 1 1 111 183 257 6 153 188 260 11 157 190 266 17 165 195 268 27 168 217 304 33 170 225 309 41 172 232 317 49 174 240 57 177 243 65 180 249 v cc3 2 2 91 178 258 19 97 204 264 23 103 210 275 35 109 216 281 43 117 221 291 51 123 226 295 59 129 230 301 67 135 236 306 73 141 241 313 79 147 247 85 160 253 mobile pentium ? processor with mmx? technology 13 1/9/98 11:56 am 24346802.doc intel confidential (until publication date) table 2. tcp pin cross reference by pin name (contd.) v ss 3 80 173 246 7 86 176 250 12 92 179 252 18 98 182 256 20 104 187 261 24 110 189 263 26 112 194 267 32 118 203 269 36 124 209 274 42 130 215 280 44 136 218 290 50 142 220 294 52 148 224 302 58 154 229 305 60 159 233 307 66 166 235 310 68 169 239 314 74 171 244 320 nc 175 184 271 note: 1. these v cc2 pins are 1.8v (166/200/233 mhz) or 2.0v (266 mhz) inputs to the core, but may change to a different voltage on future offerings of this microprocessor family. 2. all v cc3 pins are 2.5v i/o power inputs. mobile pentium ? processor with mmx? technology 14 1/9/98 11:56 am 24346802.doc intel confidential (until publication date) table 3 . tcp pin cross references by pin number (pins 1-320) pin # signal pin # signal pin # signal pin # signal 1 v cc2 41 v cc2 81 d42 121 d19 2 v cc3 42 v ss 82 d41 122 d18 3 v ss 43 v cc3 83 d40 123 v cc3 4 hold 44 v ss 84 dp4 124 v ss 5 wb/wt# 45 d60 85 v cc3 125 d17 6 v cc2 46 d59 86 v ss 126 d16 7 v ss 47 d58 87 d39 127 dp1 8 na# 48 d57 88 d38 128 d15 9 boff# 49 v cc2 89 d37 129 v cc3 10 brdy# 50 v ss 90 d36 130 v ss 11 v cc2 51 v cc3 91 v cc3 131 d14 12 v ss 52 v ss 92 v ss 132 d13 13 ken# 53 d56 93 d35 133 d12 14 ahold 54 dp6 94 d34 134 d11 15 inv 55 d55 95 d33 135 v cc3 16 ewbe# 56 d54 96 d32 136 v ss 17 v cc2 57 v cc2 97 v cc3 137 d10 18 v ss 58 v ss 98 v ss 138 d9 19 v cc3 59 v cc3 99 dp3 139 d8 20 v ss 60 v ss 100 d31 140 dp0 21 cache# 61 d53 101 d30 141 v cc3 22 m/io# 62 d52 102 d29 142 v ss 23 v cc3 63 d51 103 v cc3 143 d7 24 v ss 64 d50 104 v ss 144 d6 25 bp3 65 v cc2 105 d28 145 d5 26 vss 66 v ss 106 d27 146 d4 27 v cc2 67 v cc3 107 d26 147 v cc3 28 bp2 68 v ss 108 d25 148 v ss 29 pm1/bp1 69 d49 109 v cc3 149 d3 mobile pentium ? processor with mmx? technology 15 1/9/98 11:56 am 24346802.doc intel confidential (until publication date) table 3 . tcp pin cross references by pin number (pins 1-320) pin # signal pin # signal pin # signal pin # signal 30 pm0/bp0 70 d48 110 vss 150 d2 31 ferr# 71 dp5 111 v cc2 151 d1 32 v ss 72 d47 112 v ss 152 d0 33 v cc2 73 v cc3 113 d24 153 v cc2 34 ierr# 74 v ss 114 dp2 154 v ss 35 v cc3 75 d46 115 d23 155 picclk 36 v ss 76 d45 116 d22 156 picd0 37 dp7 77 d44 117 v cc3 157 v cc2 38 d63 78 d43 118 v ss 158 picd1 39 d62 79 v cc3 119 d21 159 v ss 40 d61 80 v ss 120 d20 160 v cc3 161 tck 201 a22 241 v cc3 281 v cc3 162 tdo 202 a23 242 a12 282 be3# 163 tdi 203 v ss 243 v cc2 283 be2# 164 tms 204 v cc3 244 v ss 284 be1# 165 v cc2 205 a24 245 a13 285 be0# 166 v ss 206 a25 246 v ss 286 a20m# 167 trst# 207 a26 247 v cc3 287 flush# 168 v cc2 208 a27 248 a14 288 buschk# 169 v ss 209 v ss 249 v cc2 289 w/r# 170 v cc2 210 v cc3 250 v ss 290 v ss 171 v ss 211 a28 251 a15 291 v cc3 172 v cc2 212 a29 252 v ss 292 hit# 173 v ss 213 a30 253 v cc3 293 hitm# 174 v cc2 214 a31 254 a16 294 v ss 175 nc 215 v ss 255 a17 295 v cc3 176 v ss 216 v cc3 256 v ss 296 ads# 177 v cc2 217 v cc2 257 v cc2 297 eads# 178 v cc3 218 v ss 258 v cc3 298 d/c# 179 v ss 219 a3 259 a18 299 pwt mobile pentium ? processor with mmx? technology 16 1/9/98 11:56 am 24346802.doc intel confidential (until publication date) table 3 . tcp pin cross references by pin number (pins 1-320) pin # signal pin # signal pin # signal pin # signal 180 v cc2 220 v ss 260 v cc2 300 pcd 181 stpclk# 221 v cc3 261 v ss 301 v cc3 182 v ss 222 a4 262 a19 302 v ss 183 v cc2 223 a5 263 v ss 303 lock# 184 bf2 224 v ss 264 v cc3 304 v cc2 185 bf1 225 v cc2 265 a20 305 v ss 186 bf 0 226 v cc3 266 v cc2 306 v cc3 187 v ss 227 a6 267 v ss 307 v ss 188 v cc2 228 a7 268 v cc2 308 ap 189 v ss 229 v ss 269 v ss 309 v cc2 190 v cc2 230 v cc3 270 reset 310 v ss 191 pen# 231 a8 271 nc 311 hlda 192 init 232 v cc2 272 clk 312 breq 193 ignne# 233 v ss 273 scyc 313 v cc3 194 v ss 234 a9 274 v ss 314 v ss 195 v cc2 235 v ss 275 v cc3 315 apchk# 196 smi# 236 v cc3 276 be7# 316 pchk# 197 intr/lint0 237 a10 277 be6# 317 v cc2 198 r/s# 238 a11 278 be5# 318 prdy 199 nmi/lint1 239 v ss 279 be4# 319 smiact# 200 a21 240 v cc2 280 v ss 320 v ss note: 1. v cc2 pins are 1.8v (166/200/233 mhz) or 2.0v (266 mhz) inputs to the core. 2. v cc3 pins are 2.5v inputs to the i/o. mobile pentium ? processor with mmx? technology 17 1/9/98 11:56 am 24346802.doc intel confidential (until publication date) 3.3. design notes for reliable operation, always connect unused inputs to an appropriate signal level. unused active low inputs should be connected to v cc3 . unused active high inputs should be connected to gnd (v ss ). no connect (nc) pins must remain unconnected. connection of nc pins may result in component failure or incompatibility with processor steppings. 3.4. quick pin reference this section gives a brief functional description of each of the pins. for a detailed description, see the hardware interface chapter in the pentium ? processor family developer's manual. note all input pins must meet their ac/dc specifications to guarantee proper functional behavior. the # symbol at the end of a signal name indicates that the active or asserted state occurs when the signal is at a low voltage. when a # symbol is not present after the signal name, the signal is active, or asserted at the high voltage level. square brackets around a signal name indicate that the signal is defined only at reset. the pins are classified as input or output based on their function in master mode. see the error detection chapter of the pentium ? processor family developer?s manual, for further information. mobile pentium ? processor with mmx? technology 18 1/9/98 11:56 am 24346802.doc intel confidential (until publication date) table 4 . quick pin reference symbol type name and function a20m# i when the address bit 20 mask pin is asserted, the mobile pentium ? processor with mmx? technology emulates the address wraparound at 1 mbyte which occurs on the 8086. when a20m# is asserted, the processor masks physical address bit 20 (a20) before performing a lookup to the internal caches or driving a memory cycle on the bus. the effect of a20m# is undefined in protected mode. a20m# must be asserted only when the processor is in real mode. a31-a3 i/o as outputs, the address lines of the processor along with the byte enables define the physical area of memory or i/o accessed. the external system drives the inquire address to the processor on a31-a5. ads# o the address status indicates that a new valid bus cycle is currently being driven by the processor. ahold i in response to the assertion of address hold , the processor will stop driving the address lines (a31-a3), and ap in the next clock. the rest of the bus will remain active so data can be returned or driven for previously issued bus cycles. ap i/o address parity is driven by the processor with even parity information on all processor generated cycles in the same clock that the address is driven. even parity must be driven back to the processor during inquire cycles on this pin in the same clock as eads# to ensure that correct parity check status is indicated. apchk# o the address parity check status pin is asserted two clocks after eads# is sampled active if the processor has detected a parity error on the address bus during inquire cycles. apchk# will remain active for one clock each time a parity error is detected. be7#-be5# be4#-be0# o i/o the byte enable pins are used to determine which bytes must be written to external memory, or which bytes were requested by the cpu for the current cycle. the byte enables are driven in the same clock as the address lines (a31 -3). bf[2:0] i the bus frequency pins determine the bus-to-core frequency ratio. bf [2:0] are sampled at reset, and cannot be changed until another non-warm (1 ms) assertion of reset. additionally, bf[2:0] must not change values while reset is active. see table 6 for bus frequency selection. in order to override the internal defaults and guarantee that the bf[2:0] inputs remain stable while reset is active, these pins should be strapped directly to or through a pullup/pulldown resistor to vcc3 or ground. drving these pins with active logic is not recommended unless stability during reset can be guaranteed. during power up, reset should be asserted prior to or ramped simultaneously with the core voltage supply to the processor. boff# i the backoff input is used to abort all outstanding bus cycles that have not yet completed. in response to boff#, the processor will float all pins normally floated during bus hold in the next clock. the processor remains in bus hold until boff# is negated, at which time the processor restarts the aborted bus cycle(s) in their entirety. [apicen] picd1 i advanced programmable interrupt controller enable enables or disables the on- chip apic interrupt controller. if sampled high at the falling edge of reset, the apic is enabled. apicen shares a pin with the picd1 signal. mobile pentium ? processor with mmx? technology 19 1/9/98 11:56 am 24346802.doc intel confidential (until publication date) table 4. quick pin reference (contd.) symbol type name and function bp[3:2] pm/bp[1:0] o the breakpoint pins (bp3-0) correspond to the debug registers, dr3-dr0. these pins externally indicate a breakpoint match when the debug registers are programmed to test for breakpoint matches. bp1 and bp0 are multiplexed with the performance monitoring pins (pm1 and pm0). the pb1 and pb0 bits in the debug mode control register determine if the pins are configured as breakpoint or performance monitoring pins. the pins come out of reset configured for performance monitoring. brdy# i the burst ready input indicates that the external system has presented valid data on the data pins in response to a read or that the external system has accepted the processor data in response to a write request. this signal is sampled in the t2, t12 and t2p bus states. breq o the bus request output indicates to the external system that the processor has internally generated a bus request. this signal is always driven whether or not the processor is driving its bus. buschk# i the bus check input allows the system to signal an unsuccessful completion of a bus cycle. if this pin is sampled active, the processor will latch the address and control signals in the machine check registers. if, in addition, the mce bit in cr4 is set, the processor will vector to the machine check exception. note: to assure that buschk# will always be recognized, stpclk# must be deasserted any time buschk# is asserted by the system, before the system allows another external bus cycle. if buschk# is asserted by the system for a snoop cycle while stpclk# remains asserted, usually (if mce=1) the processor will vector to the exception after stpclk# is deasserted. but if another snoop to the same line occurs during stpclk# assertion, the processor can lose the buschk# request. cache# o for processor-initiated cycles, the cache pin indicates internal cacheability of the cycle (if a read), and indicates a burst writeback cycle (if a write). if this pin is driven inactive during a read cycle, the processor will not cache the returned data, regardless of the state of the ken# pin. this pin is also used to determine the cycle length (number of transfers in the cycle). clk i the clock input provides the fundamental timing for the processor. its frequency is the operating frequency of the processor external bus and requires ttl levels. all external timing parameters except tdi, tdo, tms, trst# and picd0-1 are specified with respect to the rising edge of clk. this pin is 3.3v-tolerant-only on the pentium? processor with mmx? technology. note: it is recommended that clk begin 150 ms after v cc reaches its proper operating level. this recommendation is only to assure the long term reliability of the device. d/c# o the data/code output is one of the primary bus cycle definition pins. it is driven valid in the same clock as the ads# signal is asserted. d/c# distinguishes between data and code or special cycles. mobile pentium ? processor with mmx? technology 20 1/9/98 11:56 am 24346802.doc intel confidential (until publication date) table 4. quick pin reference (contd.) symbol type name and function d63-d0 i/o these are the 64 data lines for the processor. lines d7-d0 define the least significant byte of the data bus; lines d63-d56 define the most significant byte of the data bus. when the cpu is driving the data lines, they are driven during the t2, t12 or t2p clocks for that cycle. during reads, the cpu samples the data bus when brdy# is returned. dp7-dp0 i/o these are the data parity pins for the processor. there is one for each byte of the data bus. they are driven by the processor with even parity information on writes in the same clock as write data. even parity information must be driven back to the pentium processor with voltage reduction technology on these pins in the same clock as the data to ensure that the correct parity check status is indicated by the processor. dp7 applies to d63-d56; dp0 applies to d7-d0. eads# i this signal indicates that a valid external address has been driven onto the processor address pins to be used for an inquire cycle. ewbe# i the external write buffer empty input, when inactive (high), indicates that a write cycle is pending in the external system. when the processor generates a write and ewbe# is sampled inactive, the processor will hold off all subsequent writes to all e- or m-state lines in the data cache until all write cycles have completed, as indicated by ewbe# being active. ferr# o the floating-point error pin is driven active when an unmasked floating-point error occurs. ferr# is similar to the error# pin on the intel387? math coprocessor. ferr# is included for compatibility with systems using ms-dos type floating-point error reporting. flush# i when asserted, the cache flush input forces the processor to write back all modified lines in the data cache and invalidate its internal caches. a flush acknowledge special cycle will be generated by the processor indicating completion of the writeback and invalidation. note: if flush# is sampled low when reset transitions from high to low, tristate test mode is entered. hit# o the hit indication is driven to reflect the outcome of an inquire cycle. if an inquire cycle hits a valid line in either the data or instruction cache, this pin is asserted two clocks after eads# is sampled asserted. if the inquire cycle misses the cache, this pin is negated two clocks after eads#. this pin changes its value only as a result of an inquire cycle and retains its value between the cycles. hitm# o the hit to a modified line output is driven to reflect the outcome of an inquire cycle. it is asserted after inquire cycles which resulted in a hit to a modified line in the data cache. it is used to inhibit another bus master from accessing the data until the line is completely written back. hlda o the bus hold acknowledge pin goes active in response to a hold request driven to the processor on the hold pin. it indicates that the processor has floated most of the output pins and relinquished the bus to another local bus master. when leaving bus hold, hlda will be driven inactive and the processor will resume driving the bus. if the processor has a bus cycle pending, it will be driven in the same clock that hlda is de-asserted. mobile pentium ? processor with mmx? technology 21 1/9/98 11:56 am 24346802.doc intel confidential (until publication date) table 4. quick pin reference (contd.) symbol type name and function hold i in response to the bus hold request , the processor will float most of its output and input/output pins and assert hlda after completing all outstanding bus cycles. the processor will maintain its bus in this state until hold is de-asserted. hold is not recognized during lock cycles. the processor will recognize hold during reset. ierr# o the internal error pin is used to indicate internal parity errors. if a parity error occurs on a read from an internal array, the processor will assert the ierr# pin for one clock and then shutdown. ignne# i this is the ignore numeric error input. this pin has no effect when the ne bit in cr0 is set to 1. when the cr0.ne bit is 0, and the ignne# pin is asserted, the processor will ignore any pending unmasked numeric exception and continue executing floating-point instructions for the entire duration that this pin is asserted. when the cr0.ne bit is 0, ignne# is not asserted, a pending unmasked numeric exception exists (sw.es = 1), and the floating-point instruction is one of finit, fclex, fstenv, fsave, fstsw, fstcw, feni, fdisi, or fsetpm, the processor will execute the instruction in spite of the pending exception. when the cr0.ne bit is 0, ignne# is not asserted, a pending unmasked numeric exception exists (sw.es = 1), and the floating-point instruction is one other than finit, fclex, fstenv, fsave, fstsw, fstcw, feni, fdisi, or fsetpm, the processor will stop execution and wait for an external interrupt. init i the processor initialization input pin forces the processor to begin execution in a known state. the processor state after init is the same as the state after reset except that the internal caches, write buffers, and floating-point registers retain the values they had prior to init. init may not be used in lieu of reset after power up. if init is sampled high when reset transitions from high to low, the processor will perform built-in self test prior to the start of program execution. intr i an active maskable interrupt input indicates that an external interrupt has been generated. if the if bit in the eflags register is set, the processor will generate two locked interrupt acknowledge bus cycles and vector to an interrupt handler after the current instruction execution is completed. intr must remain active until the first interrupt acknowledge cycle is generated to assure that the interrupt is recognized. inv i the invalidation input determines the final cache line state (s or i) in case of an inquire cycle hit. it is sampled together with the address for the inquire cycle in the clock eads# is sampled active. ken# i the cache enable pin is used to determine whether the current cycle is cacheable or not and is consequently used to determine cycle length. when the processor generates a cycle that can be cached (cache# asserted) and ken# is active, the cycle will be transformed into a burst line fill cycle. mobile pentium ? processor with mmx? technology 22 1/9/98 11:56 am 24346802.doc intel confidential (until publication date) table 4. quick pin reference (contd.) symbol type name and function lock# o the bus lock pin indicates that the current bus cycle is locked. the processor will not allow a bus hold when lock# is asserted (but ahold and boff# are allowed). lock# goes active in the first clock of the first locked bus cycle and goes inactive after the brdy# is returned for the last locked bus cycle. lock# is guaranteed to be de-asserted for at least one clock between back-to-back locked cycles. m/io# o the memory/input-output is one of the primary bus cycle definition pins. it is driven valid in the same clock as the ads# signal is asserted. m/io# distinguishes between memory and i/o cycles. na# i an active next address input indicates that the external memory system is ready to accept a new bus cycle although all data transfers for the current cycle have not yet completed. the processor will issue ads# for a pending cycle two clocks after na# is asserted. the processor supports up to two outstanding bus cycles. nmi i the non-maskable interrupt request signal indicates that an external non- maskable interrupt has been generated. pcd o the page cache disable pin reflects the state of the pcd bit in cr3; page directory entry or page table entry. the purpose of pcd is to provide an external cacheability indication on a page-by-page basis. mobile pentium ? processor with mmx? technology 23 1/9/98 11:56 am 24346802.doc intel confidential (until publication date) pchk# o the parity check output indicates the result of a parity check on a data read. it is driven with parity status two clocks after brdy# is returned. pchk# remains low one clock for each clock in which a parity error was detected. parity is checked only for the bytes on which valid data is returned. pen# i the parity enable input (along with cr4.mce) determines whether a machine check exception will be taken as a result of a data parity error on a read cycle. if this pin is sampled active in the clock, a data parity error is detected. the processor will latch the address and control signals of the cycle with the parity error in the machine check registers. if, in addition, the machine check enable bit in cr4 is set to "1", the processor will vector to the machine check exception before the beginning of the next instruction. picclk i the apic interrupt controller serial data bus clock is driven into the programmable interrupt controller clock input of the pentium ? processor with mmx? technology. picd0-1 [apicen] i/o programmable interrupt controller data lines 0-1 of the pentium? processor with mmx? technology comprise the data portion of the apic 3-wire bus. they are open-drain outputs that require external pull-up resistor. these signals are multiplexed with apicen. pm/bp[1:0] o these pins function as part of the performance monitoring feature. the breakpoint 1-0 pins are multiplexed with the performance monitoring 1 -0 pins. the pb1 and pb0 bits in the debug mode control register determine if the pins are configured as breakpoint or performance monitoring pins. the pins come out of reset configured for performance monitoring. prdy o the probe ready output pin indicates that the processor has stopped normal execution in response to the r/s# pin going active or probe mode being entered. pwt o the page writethrough pin reflects the state of the pwt bit in cr3, the page directory entry, or the page table entry. the pwt pin is used to provide an external writeback indication on a page-by-page basis. mobile pentium ? processor with mmx? technology 24 1/9/98 11:56 am 24346802.doc intel confidential (until publication date) table 4. quick pin reference (contd.) symbol type name and function r/s# i the run/stop input is provided for use with the intel debug port. please refer to the pentium ? processor family developer?s manual (order number 241428) for more details. reset i reset forces the processor to begin execution at a known state. all the processor internal caches will be invalidated upon the reset. modified lines in the data cache are not written back. flush# and init are sampled when reset transitions from high to low to determine if tristate test mode will be entered or if bist will be run. scyc o the split cycle output is asserted during misaligned locked transfers to indicate that more than two cycles will be locked together. this signal is defined for locked cycles only. it is undefined for cycles which are not locked. smi# i the system management interrupt causes a system management interrupt request to be latched internally. when the latched smi# is recognized on an instruction boundary, the processor enters system management mode. smiact# o an active system management interrupt active output indicates that the processor is operating in system management mode. stpclk# i assertion of the stop clock input signifies a request to stop the internal clock of the pentium processor with voltage reduction technology thereby causing the core to consume less power. when the cpu recognizes stpclk#, the processor will stop execution on the next instruction boundary, unless superseded by a higher priority interrupt, and generate a stop grant acknowledge cycle. when stpclk# is asserted, the processor will still respond to external snoop requests. tck i the testability clock input provides the clocking function for the processor boundary scan in accordance with the ieee boundary scan interface (standard 1149.1). it is used to clock state information and data into and out of the processor during boundary scan. tdi i the test data input is a serial input for the test logic. tap instructions and data are shifted into the processor on the tdi pin on the rising edge of tck when the tap controller is in an appropriate state. tdo o the test data output is a serial output of the test logic. tap instructions and data are shifted out of the processor on the tdo pin on tck's falling edge when the tap controller is in an appropriate state. tms i the value of the test mode select input signal sampled at the rising edge of tck controls the sequence of tap controller state changes. trst# i when asserted, the test reset input allows the tap controller to be asynchronously initialized. vcc2 i these pins are the 1.8v (166/200/233 mhz) or 2.0v (266 mhz) power inputs to the core. mobile pentium ? processor with mmx? technology 25 1/9/98 11:56 am 24346802.doc intel confidential (until publication date) table 4. quick pin reference (contd.) symbol type name and function vcc3 i these pins are the 2.5v power inputs to the i/o. vss i these pins are the ground inputs. w/r# o write/read is one of the primary bus cycle definition pins. it is driven valid in the same clock as the ads# signal is asserted. w/r# distinguishes between write and read cycles. wb/wt# i the writeback/writethrough input allows a data cache line to be defined as writeback or writethrough on a line-by-line basis. as a result, it determines whether a cache line is initially in the s or e state in the data cache. mobile pentium ? processor with mmx? technology 26 1/9/98 11:56 am 24346802.doc intel confidential (until publication date) 3.5. bus frequency core and bus frequencies can be set according to table 5 below. each mobile pentium processor with mmx technology is specified to operate within a single bus-to-core ratio. operation in other bus- to-core ratios or outside the specified operating frequency range is not supported. table 5 . bus frequency selections (1) bf2 bf1 bf0 bus/core ratio max bus/core frequency (mhz) 0 0 0 2/5 66/166 0 0 1 1/3 66/200 0 1 1 2/7 66/233 1 0 0 1/4 66/266 notes: 1. each processor must be externally configured with the bf0-2 pins to operate in the specified bus fraction mode. operation out of the specification is not supported. mobile pentium ? processor with mmx? technology 27 1/9/98 11:56 am 24346802.doc intel confidential (until publication date) 3.6. pin refer ence tables table 6 . output pins 1 name active level when floated ads# low bus hold, boff# apchk# low be7#-be4# low bus hold, boff# breq high cache# low bus hold, boff# ferr# low hit# low hitm# 2 low hlda high ierr# low lock# low bus hold, boff# m/io#, d/c#, w/r# n/a bus hold, boff# pchk# low bp3-2, pm1/bp1, pm0/bp0 high prdy high pwt, pcd high bus hold, boff# scyc high bus hold, boff# smiact# low tdo n/a all states except shift-dr and shift-ir note: 1. all output and input/output pins are floated during tristate test mode (except tdo). 2. hitm# pin has an internal pull-up resistor. mobile pentium ? processor with mmx? technology 28 1/9/98 11:56 am 24346802.doc intel confidential (until publication date) table 7 . input pins name active level synchronous/ asynchronous internal resistor qualified a20m# low asynchronous ahold high synchronous bf0 high synchronous/reset pulld own bf1 high synchronous/reset pullup bf2 high synchronous/reset pulld own boff# low synchronous brdy# low synchronous pullup bus state t2,t12,t2p buschk# low synchronous pullup brdy# clk n/a eads# low synchronous ewbe# low synchronous brdy# flush# low asynchronous hold high synchronous ignne# low asynchronous init high asynchronous intr high asynchronous inv high synchronous eads# ken# low synchronous first brdy#/na# na# low synchronous bus state t2,td,t2p nmi high asynchronous pen# low synchronous brdy# picclk high asynchronous pullup r/s# n/a asynchronous pullup reset high asynchronous smi# low asynchronous pullup stpclk# low asynchronous pullup tck n/a pullup tdi n/a synchronous/tck pullup tck tms n/a synchronous/tck pullup tck trst# low asynchronous pullup mobile pentium ? processor with mmx? technology 29 1/9/98 11:56 am 24346802.doc intel confidential (until publication date) wb/wt# n/a synchronous first brdy#/na# table 8 . input/output pins 1 name active level when floated qualified (when an input) internal resistor a31-a3 n/a address hold, bus hold, boff# eads# ap n/a address hold, bus hold, boff# eads# be3#-be0# low bus hold, boff# reset pulldown 2 d63-d0 n/a bus hold, boff# brdy# dp7-dp0 n/a bus hold, boff# brdy# picd0 n/a pullup picd1[apicen] n/a pulldown notes: 1. all output and input/output pins are floated during tristate test mode (except tdo). 2. be3#-be0# have pulldowns during reset only. mobile pentium ? processor with mmx? technology 30 1/9/98 11:56 am 24346802.doc intel confidential (until publication date) 3.7 . pin grouping according to function table 9 organizes the pins with respect to their function. table 9 . pin functional grouping function pins clock clk initialization reset, init, bf[2:0] address bus a31-a3, be7# - be0# address mask a20m# data bus d63-d0 address parity ap, apchk# apic support picclk, picd0-1 data parity dp7-dp0, pchk#, pen# internal parity error ierr# system error buschk# bus cycle definition m/io#, d/c#, w/r#, cache#, scyc, lock# bus control ads#, brdy#, na# page cacheability pcd, pwt cache control ken#, wb/wt# cache snooping/consistency ahold, eads#, hit#, hitm#, inv cache flush flush# write ordering ewbe# bus arbitration boff#, breq, hold, hlda interrupts intr, nmi floating-point error reporting ferr#, ignne# system management mode smi#, smiact# tap port tck, tms, tdi, tdo, trst# breakpoint/performance monitoring pm0/bp0, pm1/bp1, bp3-2 clock control stpclk# debugging r/s#, prdy mobile pentium ? processor with mmx? technology 31 1/9/98 11:56 am 24346802.doc intel confidential (until publication date) 4.0. electrical specifications 4.1. absolute maximum ratings the following values are stress ratings only. functional operation at the maximum ratings is not implied nor guaranteed. functional operating conditions are given in the ac and dc specification tables. extended exposure to the maximum ratings may affect device reliability. furthermore, although the mobile pentium processor with mmx technology contains protective circuitry to resist damage from electrostatic discharge (esd), always take precautions to avoid high static voltages or electric fields. case temperature under bias ......... - 65 c to 110 c storage temperature ....................... - 65 c to 150 c v cc3 supply voltage with respect to v ss .......................... - 0.5v to +3.2v v cc2 supply voltage with respect to v ss .......................... - 0.5v to +2.8v 2.5v only buffer dc input voltage ................................ ... - 0.5v to v cc3 +0.5v* *not to exceed v cc3 max warning stressing the device beyond the "absolute maximum ratings" may cause permanent damage. these are stress ratings only. operation beyond the "operating conditions" is not recommended and extended exposure beyond the "operating conditions" may affect device reliability. 4.2. dc specifications tables 10, 11, 12 and 13 list the dc specifications which apply to the mobile pentium processor with mmx technology on 0.25 micron . the processor core operates at 1.8v (166/200/233 mhz) or 2.0v (266 mhz) internally while the i/o interface operates at 2.5v. 4.2.1. power sequencing there is no specific sequence required for powering up or powering down the v cc2 and v cc3 power supplies. however, for compatibility with future mobile processors, it is recommended that the v cc2 and v cc3 power supplies be either both on or both off within one second of each other. table 10 . v cc and t case specifications package tcase supply min voltage max voltage voltage tolerance frequency tcp 0 to 95oc vcc2 1.665v 1.850v 1.935v 2.150v 1.8v +/- 0.135v 2.0v +/- 0.150v 166/200/233 mhz 266 mhz vcc3 2.375v 2.625v 2.5v +/- 0.125v 166/200/233/266 mhz mobile pentium ? processor with mmx? technology 32 1/9/98 11:56 am 24346802.doc intel confidential (until publication date) table 11 . dc specifications 1 symbol parameter min max unit notes v il3 input low voltage -0.3 0.5 v v ih3 input high voltage v cc3 - 0.7 v cc3 + 0.3 v ttl level v ol3 output low voltage 0.4 v ttl level 1 v oh3 output high voltage v cc3 - 0.4 v cc3 - 0.2 v v ttl level 2 ttl level 3 notes: 1. parameter measured at -4 ma.. 2. parameter measured at 3 ma. 3. parameter measured at 1ma; not 100% tested, guaranteed by design. table 12 . i cc specifications symbol parameter min max unit notes i cc2 power supply current 2.35 2.70 3.10 4.00 a a a a 166 mhz 1 200 mhz 1 233 mhz 1 266 mhz 1 i cc3 power supply current 0. 33 0.33 0.38 0.38 a a a a 166 mhz 1 200 mhz 1 233 mhz 1 266 mhz 1 note: 1. this value should be used for power supply design. it was determined using a worst case instruction mix and maximum v cc at tcase = 0c. power supply transient response and decoupling capacitors must be sufficient to handle the instantaneous current changes occurring during transitions from stop clock to full active modes. mobile pentium ? processor with mmx? technology 33 1/9/98 11:56 am 24346802.doc intel confidential (until publication date) table 13 . power dissipation requirements for thermal design parameter typical 1 max 2 unit frequency notes thermal design power 4.1 5.0 5.5 7.6 watts watts watts watts 166 mhz 200 mhz 233 mhz 266 mhz active power 5 2.3 2.7 3.0 4.5 watts watts watts watts 166 mhz 200 mhz 233 mhz 266 mhz stop grant / auto halt powerdown power dissipation 3 0.42 0.46 0.53 0.70 watts watts watts watts 166 mhz 200 mhz 233 mhz 266 mhz stop clock power 4 0.02 0.02 0.02 0.05 0.05 0.05 0.06 watts watts watts watts 166 mhz 200 mhz 233 mhz 266 mhz notes: 1. this is the typical power dissipation in a system. this value is expected to be the average value that will be measured in a system using a typical device at v cc2 = 1.8v (166/200/233 mhz) or 2.0v (266 mhz) running typical applications. this value is highly dependent upon the specific system configuration. typical power specifications are not tested. 2. systems must be designed to thermally dissipate the maximum thermal design power unless the system uses thermal feedback to limit processor?s maximum power. the maximum thermal design power is determined using a worst-case instruction mix with v cc2 = 1.8v (166/200/233 mhz) or 2.0v (266 mhz) and also takes into account the thermal time constant of the package. 3. stop grant/auto halt powerdown power dissipation is determined by asserting the stpclk# pin or executing the halt instruction. when in this mode, the processor has a new feature which allows it to power down additional circuitry to enable lower power dissipation. this is the power without snooping at vcc2 = 1.8v/2.0v and with tr12 bit 21 set. in order to enable this feature, tr12 bit 21 must be set to 1 (the default is 0 or disabled). stop grant/auto halt powerdown power dissipation without tr12 bit21 set may be higher. the max rating may be changed in future spec update. 4. stop clock power dissipation is determined by asserting the stpclk# pin and then removing the external clk input. this is specified at a tcase of 50 oc. 5. active power is the average power measured in a system using a typical device running typical applications under normal operating conditions at nominal vcc and room temperature. mobile pentium ? processor with mmx? technology 34 1/9/98 11:56 am 24346802.doc intel confidential (until publication date) table 14 . input and output characteristics symbol parameter min max unit notes c in input capacitance 15 pf 4 c o output capacitance 20 pf 4 c i/o i/o capacitance 25 pf 4 c clk clk input capacitance 15 pf 4 c tin test input capacitance 15 pf 4 c tout test output capacitance 20 pf 4 c tck test clock capacitance 15 pf 4 i li input leakage current 15 m a 0 mobile pentium ? processor with mmx? technology 36 1/9/98 11:56 am 24346802.doc intel confidential (until publication date) table 15. mobile pentium? processor with mmx? technology on 0.25 micron ac specifications for 66-mhz bus operation see table 10 for v cc and t case specifications, cl = 0 pf symbol parameter min max unit figure notes clk frequency 33.33 66.66 mhz 23 t 1a clk period 15.0 30.0 ns 3 t 1b clk period stability 250 ps 1, 19 t 2 clk high time 4.0 ns 3 @ v cc3 - 0.7v, (1) t 3 clk low time 4.0 ns 3 @ 0.5v, (1) t 4 clk fall time 0.15 1.5 ns 3 (v cc3 - 0.7v to 0.5v), (1, 5) t 5 clk rise time 0.15 1.5 ns 3 (0.5v to v cc3 ? 0.7v), (1, 5) t 6a pwt, pcd, cache# valid delay 1.0 7.0 ns 4 t 6b ap valid delay 1.0 8.5 ns 4 t 6c lock# valid delay 0.9 7.0 ns 4 t 6d ads# valid delay 1.0 6.2 ns 4 t 6e a3-a31 valid delay 0.8 6.4 ns 4 t 6f m/io# valid delay 0.8 6.2 ns 4 t 6g be0-7#, d/c#, w/r#, scyc valid delay 0.8 7.0 ns 4 t 7 ads#, ap, a3-a31, pwt, pcd, be0-7#, m/io#, d/c#, w/r#, cache#, scyc, lock# float delay 10.0 ns 5 1 t 8a apchk#, ierr#, ferr# valid delay 1.0 8.3 ns 4 4 mobile pentium ? processor with mmx? technology 37 1/9/98 11:56 am 24346802.doc intel confidential (until publication date) table 15. mobile pentium? processor with mmx? technology on 0.25 micron ac specifications for 66-mhz bus operation (contd.) see table 10 for v cc and t case specifications, c l = 0 pf symbol parameter min max unit figure notes t 8b pchk# valid delay 1.0 7.0 ns 4 4 t 9a breq valid delay 1.0 8.0 ns 4 4 t 9b smiact# valid delay 1.0 7.3 ns 4 4 t 9c hlda valid delay 1.0 6.8 ns 4 4 t 10a hit# valid delay 1.0 6.8 ns 4 t 10b hitm# valid delay 0.9 6.0 ns 4 t 11a pm0-1, bp0-3 valid delay 1.0 10.0 ns 4 t 11b prdy valid delay 1.0 8.0 ns 4 t 12 d0-d63, dp0-7 write data valid delay 1.0 7.7 ns 4 t 13 d0-d63, dp0-3 write data float delay 10.0 ns 5 1 t 14 a5-a31 setup time 6.0 ns 6 20 t 15 a5-a31 hold time 1.0 ns 6 t 16a inv, ap setup time 5.0 ns 6 t 16b eads# setup time 5.0 ns 6 t 17 eads#, inv, ap hold time 1.0 ns 6 t 18a ken# setup time 5.0 ns 6 t 18b na#, wb/wt# setup time 4.5 ns 6 t 19 ken#, wb/wt#, na# hold time 1.0 ns 6 t 20 brdy# setup time 4.75 ns 6 t 21 brdy# hold time 1.0 ns 6 t 22 ahold, boff# setup time 5.5 ns 6 t 23 ahold, boff# hold time 1.0 ns 6 t 24a buschk#, ewbe#, hold setup time 5.0 ns 6 t 24b pen# setup time 4.8 ns 6 t 25a buschk#, ewbe#, pen# hold time 1.0 ns 6 t 25b hold hold time 1.5 ns 6 mobile pentium ? processor with mmx? technology 38 1/9/98 11:56 am 24346802.doc intel confidential (until publication date) table 15. mobile pentium? processor with mmx? technology on 0.25 micron ac specifications for 66-mhz bus operation (contd.) see table 10 for v cc and t case specifications, c l = 0 pf symbol parameter min max unit figure notes t 26 a20m#, intr, stpclk# setup time 5.0 ns 6 11, 15 t 27 a20m#, intr, stpclk# hold time 1.0 ns 6 12 t 28 init, flush#, nmi, smi#, ignne# setup time 5.0 ns 6 11, 15, 16 t 29 init, flush#, nmi, smi#, ignne# hold time 1.0 ns 6 12 t 30 init, flush#, nmi, smi#, ignne# pulse width, async 2.0 clks 14, 16 t 31 r/s# setup time 5.0 ns 6 11, 15, 16 t 32 r/s# hold time 1.0 ns 6 12 t 33 r/s# pulse width, async. 2.0 clks 14, 16 t 34 d0-d63, dp0-7 read data setup time 2.8 ns 6 t 35 d0-d63, dp0-7 read data hold time 1.5 ns 6 t 36 reset setup time 5.0 ns 7 11, 15 t 37 reset hold time 1.0 ns 7 12 t 38 reset pulse width, v cc & clk stable 15.0 clks 7 16 t 39 reset active after v cc & clk stable 1.0 ms 7 power up t 40 reset configuration signals (init, flush#) setup time 5.0 ns 7 11, 15, 16 t 41 reset configuration signals (init, flush#) hold time 1.0 ns 7 12 t 42a reset configuration signals (init, flush#) setup time, async. 2.0 clks 7 to reset falling edge (15) t 42b reset configuration signals (init, flush#) hold time, async.. 2.0 clks 7 to reset falling edge mobile pentium ? processor with mmx? technology 39 1/9/98 11:56 am 24346802.doc intel confidential (until publication date) table 15. mobile pentium? processor with mmx? technology on 0.25 micron ac specifications for 66-mhz bus operation (contd.) see table 10 for v cc and t case specifications, c l = 0 pf symbol parameter min max unit figure notes t 43b bf0-bf2 hold time 2.0 clks 7 to reset falling edge (18) t 43c apicen, be4# setup time 2.0 clks 7 to reset falling edge t 43d apicen, be4# hold time 2.0 clks 7 to reset falling edge t 44 tck frequency 16.0 mhz t 45 tck period 62.5 ns 3 t 46 tck high time 25.0 ns 3 @ vcc3 - 0.7v (1) t 47 tck low time 25.0 ns 3 @ 0.5v (1) t 48 tck fall time 5.0 ns 3 (vcc3-0.7v to 0.5v (1, 8, 9) t 49 tck rise time 5.0 ns 3 (0.5v to vcc3 - 0.7v) (1, 8, 9) t 50 trst# pulse width 40.0 clks 9 asynchronous(1) t 51 tdi, tms setup time 5.0 ns 8 7 t 52 tdi, tms hold time 13.0 ns 8 7 t 53 tdo valid delay 3.0 20.0 ns 8 8 t 54 tdo float delay 25.0 ns 8 1, 8 t 55 all non-test outputs valid delay 3.0 20.0 ns 8 3, 8, 10 t 56 all non-test outputs float delay 25.0 ns 8 1, 3, 8, 10 t 57 all non-test inputs setup time 5.0 ns 8 3, 7, 10 t 58 all non-test inputs hold time 13.0 ns 8 3, 7, 10 mobile pentium ? processor with mmx? technology 40 1/9/98 11:56 am 24346802.doc intel confidential (until publication date) table 16. mobile pentium? processor with mmx? technology on 0.25 micron apic ac specifications symbol parameter min max unit figure notes t 60a picclk frequency 2.0 16.66 mhz t 60b picclk period 60 500 ns 3 t 60c picclk high time 15 ns 3 t 60d picclk low time 15 ns 3 t 60e picclk rise time 0.15 2.5 ns 3 t 60f picclk fall time 0.15 2.5 ns 3 t 60g picd0-1 setup time 3 ns 6 to picclk t 60h picd0-1 hold time 2.5 ns 6 to picclk t 60i picd0-1 valid delay (l to h) 4 38 ns 4 from picclk, 21 t 60j picd0-1 high time (h to l) 4 22 ns 4 from picclk, 21 t 61 picclk setup time 5.0 ns 6 to clk t 62 picclk hold time 2.0 ns 6 to clk t 63 picclk ratio (clk/picclk) 4 22 mobile pentium ? processor with mmx? technology 41 1/9/98 11:56 am 24346802.doc intel confidential (until publication date) notes for tables 15 and 16: notes 2, 6, and 14 are general and apply to all standard ttl signals used with the pentium ? processor family. 1. not 100% tested. guaranteed by design/characterization. 2. ttl input test waveforms are assumed to be 0 to 2.5v transitions with 1v/ns rise and fall times. 3. non-test outputs and inputs are the normal output or input signals (besides tck, trst#, tdi, tdo, and tms). these timings correspond to the response of these signals due to boundary scan operations. 4. apchk#, ferr#, hlda, ierr#, lock#, and pchk# are glitch-free outputs. glitch-free signals monotonically transition without false transitions (i.e., glitches). 5. 0.87v/ns clk input rise/fall time 8.7v/ns. 6. 0.3v/ns input rise/fall time 5v/ns. 7. referenced to tck rising edge. 8. referenced to tck falling edge. 9. 1 ns can be added to the maximum tck rise and fall times for every 10 mhz of frequency below 33 mhz. 10. during probe mode operation , do not use the boundary scan timings (t 55-58 ). 11. setup time is required to guarantee recognition on a specific clock. 12. hold time is required to guarantee recognition on a specific clock. 13. all ttl timings are referenced from v cc3 /2. 14. to guarantee proper asynchronous recognition, the signal must have been de-asserted (inactive) for a minimum of 2 clocks before being returned active and must meet the minimum pulse width. 15. this input may be driven asynchronously. 16. when driven asynchronously, reset, nmi, flush#, r/s#, init, and smi# must be de-asserted (inactive) for a minimum of 2 clocks before being returned active. 17. the d/c#, m/io#, w/r#, cache#, and a5-a31 signals are sampled only on the clk that ads# is active. 18. bf[2:0] must not change values while reset is active. in order to override the internal defaults and guarantee that the bf[2:0] inputs remain stable while reset is active, these pins should be strapped directly to or through a pullup/pulldown resistor to vcc3 or ground. driving these pins with active logic is not recommended unless stability during reset can be guaranteed. 19. these signals are measured on the rising edge of adjacent clks at v cc3 /2. to ensure a 1:1 relationship between the amplitude of the input jitter and the internal and external clocks, the jitter frequency spectrum should not have any power spectrum peaking between 500 khz and 1/3 of the clk operating frequency. the amount of jitter present must be accounted for as a component of clk skew between devices. the internal clock generator requires a constant frequency clk input to within 250ps. therefore, the clk input cannot be changed dynamically. 20. timing (t14) is required for external snooping (e.g., address setup to the clk in which eads# is sampled active). 21. this assumes an external pullup resistor to vcc and a lumped capacitive load. the pullup resistor must be between 300 ohms and 1k ohms, the capacitance must be between 20pf and 120pf, and the rc product must be between 6ns and 36ns. 22. the clk to picclk ratio has to be an integer and the ratio (clk/picclk) cannot be smaller than 4. 23. clk input frequency must be either 33.33 mhz (+1 mhz) or 66.66 mhz (-1 mhz). operations in the range between 33.33 mhz and 66.6 mhz is not supported. * each valid delay is specified for a 0 pf load. the system designer should us e i/o buffer modeling to account for signal flight time delays. mobile pentium ? processor with mmx? technology 42 1/9/98 11:56 am 24346802.doc intel confidential (until publication date) pp0051 t x t w t y t z t v t v t w t x t y t z = = = = = t5, t49, t60e t4, t48, t60f t2, t46, t60c t1, t45, t60b t3, t47, t60d vcc3-0.7v 0.5v figure 3 . clock waveform pp0052 t x = t6, t8, t9, t10, t11, t12, t60i signal valid t max. x t min. x vcc3/2 vcc3/2 figure 4 . valid delay timings mobile pentium ? processor with mmx? technology 43 1/9/98 11:56 am 24346802.doc intel confidential (until publication date) signal vcc3/2 t y t x t x = t7, t13 t y = t6min, t12min figure 5 . float delay timings clk signal valid vcc3/2 t x = t14, t16, t18, t20, t22, t24, t26, t28, t31, t34, t60g (to picclk), t61 t y = t15, t17, t19, t21, t23, t25, t27, t29, t32, t35, t60h (to picclk), t62 t y t x figure 6 . setup and hold timings mobile pentium ? processor with mmx? technology 44 1/9/98 11:56 am 24346802.doc intel confidential (until publication date) clk reset config vcc3/2 vcc3/2 t z t t = t40 t v t t t u t x t w t y t u = t v = t37 w = x = t43b, t43d, t43f, t88 y = t z = t36 valid t41 t t t t38, t39 t42, t43c, t43e, t87 figure 7 . reset and configuration timings mobile pentium ? processor with mmx? technology 45 1/9/98 11:56 am 24346802.doc intel confidential (until publication date) vcc3/2 t r = t57 tck tdi tms tdo output signals input signals t v t w t x t y t r t s t u t z t s = t58 t u = t54 t v = t51 t w = t52 t x = t53 t y = t55 t z = t56 figure 8 . test timings vcc3/2 trst# t x = t50 t x figure 9 . test reset timings mobile pentium ? processor with mmx? technology 46 1/9/98 11:56 am 24346802.doc intel confidential (until publication date) 4.4. i/o buffer models this section describes the i/o buffer models of the mobile pentium processor with mmx technology on 0.25 micron. the first order i/o buffer model is a simplified representation of the complex input and output buffers used. figure 10 shows the structure of the input buffer model and figure 11 shows the output buffer model. tables 17 and 18 show the parameters used to specify these models. although simplified, these buffer models will accurately model flight time and signal quality. for these parameters, there is very little added accuracy in a complete transistor model. in addition to the input and output buffer parameters, input protection diode models are provided for added accuracy. these diodes have been optimized to provide esd protection and provide some level of clamping. although the diodes are not required for simulation, it may be more difficult to meet specifications without them. note, however, some signal quality specifications require that the diodes be removed from the input model. the series resistors (r s ) are a part of the diode model. remove these when removing the diodes from the input model. mobile pentium ? processor with mmx? technology 47 1/9/98 11:56 am 24346802.doc intel confidential (until publication date) figure 10 . first order input buffer model mobile pentium ? processor with mmx? technology 48 1/9/98 11:56 am 24346802.doc intel confidential (until publication date) table 17. parameters used in the specification of the first order input buffer model parameter description cin minimum and maximum value of the capacitance of the input buffer model lp minimum and maximum value of the package inductance cp minimum and maximum value of the package capacitance rs diode series resistance d1, d2 ideal diodes pp0061 figure 11 . first order output buffer model table 18. parameters used in the specification of the first order output buffer model parameter description dv/dt minimum and maximum value of the rate of change of the open circuit voltage source used in the output buffer model r o minimum and maximum value of the output impedance of the output buffer model c o minimum and maximum value of the capacitance of the output buffer model l p minimum and maximum value of the package inductance c p minimum and maximum value of the package capacitance mobile pentium ? processor with mmx? technology 49 1/9/98 11:56 am 24346802.doc intel confidential (until publication date) 4.4.1. buffer model parameters this section gives the parameters for each input, output and bidirectional buffers. the input, output and bidirectional buffer values of the processor are listed in table 20. these tables contain listings for all three types, do not get them confused during simulation. when a bidirectional pin is operating as an input, use the c in , c p and l p values; if it is operating as a driver, use all of the data parameters. please refer to table 19 for th e groupings of the buffers. the input, output and bi-directional buffer?s values are listed below. these tables contain listings for all three types. when a bi-directional pin is operating as an input, just use the c in , c p and l p values, if it is operating as a driver use all the data parameters. table 19. tcp signal to buffer type signals type driver buffer type receiver buffer type a20m#, ahold, bf, boff#, brdy#, buschk#, eads#, ewbe#, flush#, hold, ignne#, init, intr, inv, ken#, na#, nmi, pen#, picclk, r/s#, reset, smi#, stpclk#, tck, tdi, tms, trst#, wb/wt# i er1 apchk#, be[7:5]#, bp[3:2], breq, ferr#, ierr#, pcd, pchk#, pm0/bp0, pm1/bp1, prdy, pwt, smiact#, tdo o ed1 a[31: 3], ap, be[4:0]#, cache#, d/c#, d[63:0], dp[8:0], hlda, lock#, m/io#, scyc, ads#, hitm#, hit#, w/r#, picd0, picd1 i/o eb1 eb1 mobile pentium ? processor with mmx? technology 50 1/9/98 11:56 am 24346802.doc intel confidential (until publication date) table 20 . input, output and bi-directional buffer model parameters for tcp buffer type tran si - tion dv/dt (v/nsec) r o (ohms) c p (pf) l p (nh) c o /c in (pf) min max min max min max min max min max er1 rising 0. 2 0. 4 6.4 11.3 0.8 1.2 (input) falling 0. 2 0. 4 6.4 11.3 0.8 1.2 ed1 rising 2.2/2.2 2.7/0.15 29 65 0.2 0.5 5.4 11.7 2.0 2.6 (output) falling 2.2/2.9 2.7/0.22 25 75 0.2 0.5 5.4 11.7 2.0 2.6 eb1 rising 2.2/2.2 2.7/0.15 29 65 0.2 0.4 5.2 10.3 2.0 2.6 (bidir) falling 2.2/2.9 2.7/0.22 25 75 0.2 0.4 5.2 10.3 2.0 2.6 table 21. input buffer model parameters: d (diodes) symbol parameter d1 d2 is saturation current 1.4e-14a 2.78e-16a n emission coefficient 1.19 1.00 rs series resistance 6.5 ohms 6.5 ohms tt transit time 3 ns 6 ns vj pn potential 0.983v 0.967v cj0 zero bias pn capacitance 0.281 pf 0.365 pf m pn grading coefficient 0.385 0.376 mobile pentium ? processor with mmx? technology 51 1/9/98 11:56 am 24346802.doc intel confidential (until publication date) 4.4.2. signal quality specifications signals driven by the system into the mobile pentium processor with mmx technology on 0.25 micron must meet signal quality specifications to guarantee that the components read data properly and to ensure that incoming signals do not affect the reliability of the component. there are two signal quality parameters: ringback and settling time. see section 4.4.2.3 for clk signal quality specification. 4.4.2.1. ringback excessive ringback can contribute to long-term reliability degradation of the processor, and can cause false signal detection. ringback is simulated at the input pin of a component using the input buffer model. ringback can be simulated with or without the diodes that are in the input buffer model. ringback is the absolute value of the maximum voltage at the receiving pin below v cc3 (or above v ss ) relative to v cc3 (or v ss ) level after the signal has reached its maximum voltage level. the input diodes are assumed present. maximum ringback on inputs = 0.5v ( falling edge) maximum ringback on inputs = 0.7v (rising edge ) (with diodes) if simulated without the input diodes, follow the maximum overshoot/undershoot specification. by meeting the overshoot/undershoot specification, the signal is guaranteed not to ringback excessively. if simulated with the diodes present in the input model, follow the maximum ringback specification. overshoot (undershoot) is the absolute value of the maximum voltage above v cc3 (below v ss ). the guideline assumes the absence of diodes on the input. figure 12 . overshoot/undershoot and ringback guidelines mobile pentium ? processor with mmx? technology 52 1/9/98 11:56 am 24346802.doc intel confidential (until publication date) 4.4.2.2. settling time the settling time is defined as the time a signal requires at the receiver to settle within 10 percent of v cc3 or v ss . settling time is the maximum time allowed for a signal to reach within 10 percent of its final value. most available simulation tools are unable to simulate settling time so that it accurately reflects silicon measurements. on a physical board, second-order effects and other effects serve to dampen the signal at the receiver. because of all these concerns, settling time is a recommendation or a tool for layout tuning and not a specification. settling time is simulated at the slow corner, to make sure that there is no impact on the flight times of the signals if the waveform has not settled. settling time may be simulated with the diodes included or excluded from the input buffer model. if diodes are included, settling time recommendation will be easier to meet. although simulated settling time has not shown good correlation with physical, measured settling time, settling time simulations can still be used as a tool to tune layouts. use the following procedure to verify board simulation and tuning with concerns for settling time. simulate settling time at the slow corner for a particular signal. if settling time violations occur (signal requires more than 12.5 ns. to settle to + 10 percent of its final value), simulate signal trace with d.c. diodes in place at the receiver pin. the d.c. diode behaves almost identically to the actual (non-linear) diode on the part as long as excessive overshoot does not occur. if settling time violations still occur, simulate flight times for five consecutive cycles for that particular signal. if flight time values are consistent over the five simulations, settling time should not be a concern. if however, flight times are not consistent over the five simulations, tuning of the layout is required. note that, for signals that are allocated two cycles for flight time, the recommended settling time is doubled. maximum settling time to within 10% of v ih or v il is: 12.5 ns at 66 mhz vih max + 10% 2.5 volts vih min - 10% figure 13 . settling time mobile pentium ? processor with mmx? technology 53 1/9/98 11:56 am 24346802.doc intel confidential (until publication date) 4.4.2.3. signal quality specification the maximum overshoot, maximum undershoot, overshoot threshold duration, undershoot threshold duration, and maximum ringback specifications for clk are described below: maximum overshoot and maximum undershoot specification: the maximum overshoot of the clk signals should not exceed v cc3 ,nominal + 0.6v. the maximum undershoot of the clk signals must not drop below -0.6v. overshoot threshold duration specification: the overshoot threshold duration is defined as the sum of all time during which the clk signal is above v cc3 ,nominal + 0.3v within a single clock period. the overshoot threshold duration must not exceed 20 percent of the period. undershoot threshold duration specification: the undershoot threshold duration is defined as the sum of all time during which the clk signal is below -0.3v within a single clock period. the undershoot threshold duration must not exceed 20 percent of the period. maximum ringback specification: the maximum ringback of clk associated with their high states (overshoot) must not drop below v cc3 - 0.7v as shown in figure 15 . similarly, the maximum ringback of clk associated with their low states (undershoot) must not exceed 0.5v as shown in figure 17 . refer to table 22 and table 23 for a summary of the clock overshoot and undershoot specifications for the 200- and 233 mhz pentium processor with mmx technology. table 22. overshoot specification summary specification name value units notes threshold level v cc 3,nominal + 0.3 (clk & picclk) v cc 3,nominal + 0.5 (all other inputs) v 1,2 maximum overshoot level v cc 3,nominal + 0.6 (clk & picclk) v cc 3,nominal + 1.0 (all other inputs) v 1,2 maximum threshold duration 20% of clock period above threshold voltage ns 2 maximum ringback v cc 3,nominal - 0.7 v 1,2 notes: 1. v cc3 , nominal refers to the voltage measured at the bottom side of the v cc 3 pins. see section 4.3.1 . for details. 2. see figures 14 and 15 . mobile pentium ? processor with mmx? technology 54 1/9/98 11:56 am 24346802.doc intel confidential (until publication date) table 23. undershoot specification summary specification name value units notes threshold level - 0.3 (clk & picclk) - 0.5 (all other inputs) v see figures 18 & 19 minimum undershoot level - 0.6 (clk & picclk) - 1.0 (all other inputs) v see figures 18 & 19 maximum threshold duration 20% of clock period below threshold voltage ns see figures 18 & 19 maximum ringback 0.5 v see figures 18 & 19 mobile pentium ? processor with mmx? technology 55 1/9/98 11:56 am 24346802.doc intel confidential (until publication date) 4.4.3. clock signal measurement methodology : the waveform of the clock signals should be measured at the bottom side of the processor pins using an oscilloscope with a 3 db bandwidth of at least 20 mhz (100 ms/s digital sampling rate). there should be a short isolation ground lead attached to a processor pin on the bottom side of the board. an 1 mohm probe with loading of less than 1 pf (e.g., tektronics 6243 or tektronics 6245) is recommended. the measurement should be taken at the clk (ak18) pin and its nearest v ss pin (am18). maximum overshoot, maximum undershoot and maximum ringback specifications: the display should show continuous sampling (e.g., infinite persistence) of the waveform at 500 mv/div and 5 ns/div for a recommended duration of approximately five seconds. adjust the vertical position to measure the maximum overshoot and associated ringback with the largest possible granularity. similarly, readjust the vertical position to measure the maximum undershoot and associated ringback. there is no allowance for crossing the maximum overshoot, maximum undershoot or maximum ringback specifications. overshoot threshold duration specification: a snapshot of the clock signal should be taken at 500 mv/div and 500 ps/div. adjust the vertical position and horizontal offset position to view the threshold duration. the overshoot threshold duration is defined as the sum of all time during which the clock signal is above v cc3 ,nominal + 0.3v within a single clock period. the overshoot threshold duration must not exceed 20 percent of the period. undershoot threshold duration specification: a snapshot of the clock signal should be taken at 500 mv/div and 500 ps/div. adjust the vertical position and horizontal offset position to view the threshold duration. the undershoot threshold duration is defined as the sum of all time during which the clock signal is below - 0.3v within a single clock period. the undershoot threshold duration must not exceed 20 percent of the period. these overshoot and undershoot specifications are illustrated graphically in figures 14 through 17 . overshoot threshold level maximum overshoot level overshoot threshold duration v cc3 , nominal figure 14 . maximum overshoot level, overshoot threshold level, and overshoot threshold duration mobile pentium ? processor with mmx? technology 56 1/9/98 11:56 am 24346802.doc intel confidential (until publication date) maximum ringback v cc3 , nominal figure 15 . maximum ringback associated with the signal high state maximum undershoot level undershoot threshold level undershoot threshold duration v ss ,nominal figure 16 . maximum undershoot level, undershoot threshold level, and undershoot threshold duration mobile pentium ? processor with mmx? technology 57 1/9/98 11:56 am 24346802.doc intel confidential (until publication date) maximum ringback v ss , nominal figure 17 . maximum ringback associated with the signal low state 5.0. mechanical specifications today's portable computers face the challenge of meeting desktop performance in an environment that is constrained by thermal, mechanical and electrical design considerations. these considerations have driven the development and implementation of intel?s tape carrier package (tcp). the intel tcp has been designed to offer a high pin count, low profile, reduced footprint package with uncompromised thermal and electrical performance. intel continues to provide packaging solutions that meet our rigorous criteria for quality and performance. key features of the tcp include: surface mount technology design, lead pitch of 0.25 mm, polyimide body size of 24 mm and polyimide up for pick-and- place handling. tcp components are shipped with the leads flat in slide carriers, and are designed to be excised and lead formed at the customer manufacturing site. recommendations for the manufacture of this package are included in the 1996 packaging databook (order number 240800 ) or at www.intel.lv/design/packtech/chap12.pdf. figure 18 shows a cross-section view of the tcp as mounted on the printed circuit board. figures 19 and 20 show the tcp as shipped in its slide carrier, and key dimensions of the carrier and package. figure 21 shows a cross-section detail of the package. figure 22 shows an enlarged view of the outer lead bond area of the package. mobile pentium ? processor with mmx? technology 58 1/9/98 11:56 am 24346802.doc intel confidential (until publication date) 5.1. tcp mechanical diagrams encapsulant polyimide support ring tab lead (ofc copper) polyimide keeper bar gold bump thermally conductive adhesive thermal vias ground plane 1/2 cross-section pcb full cross-section note: sketches not to scale pcb pcb 255703 figure 18 . cross-sectional view of the mounted tcp mobile pentium ? processor with mmx? technology 59 1/9/98 11:56 am 24346802.doc intel confidential (until publication date) 255705 mobile pentium ? processor with mmx? technology 60 1/9/98 11:56 am 24346802.doc intel confidential (until publication date) figure 19 . one tcp site in carrier (bottom view of die) 255706 figure 20 . one tcp site in carrier (top view of die) mobile pentium ? processor with mmx? technology 61 1/9/98 11:56 am 24346802.doc intel confidential (until publication date) 255707 figure 21 . one tcp site (cross-sectional detail) mobile pentium ? processor with mmx? technology 62 1/9/98 11:56 am 24346802.doc intel confidential (until publication date) 255708 figure 22 . outer lead bond (olb) window detail mobile pentium ? processor with mmx? technology 63 1/9/98 11:56 am 24346802.doc intel confidential (until publication date) table 24. tcp key dimensions symbol description dimension n leadcount 320 leads w tape width 48.18 0.12 l site length (43.94) reference only t test pad pitch 0.40 nominal e1 outer lead pitch 0.25 nominal b outer lead width 0.10 0.01 d1,e1 package body size 24.0 0.1 a2 package height 0.597 0.030 dl die length 10.450 +/- 0.015 dw die width 9.088 +/- 0.015 lt lead thickness 0.025 mm el encap length 11.053 +/- 0.015 ew encap width 9.691 +/- 0.015 notes: dimensions are in millimeters unless otherwise noted. dimensions in parentheses are for reference only. table 25. mounted tcp dimensions symbol description dimension a package height 0.75 maximum d, e terminal dimension 29.5 nominal wt package weight 0.5 g maximum note: dimensions are in millimeters unless otherwise noted. package terminal dimension (lead tip-to-lead tip) assumes the use of a keeper bar. mobile pentium ? processor with mmx? technology 64 1/9/98 11:56 am 24346802.doc intel confidential (until publication date) 6.0. thermal specifications the mobile pentium processor with mmx technology on 0.25 micron is specified for proper operation when the case temperature, t case (t c ), for tcp is within the specified range of 0 c to 95 c. 6.1. measuring thermal values for tcp to verify that the proper t c (case temperature) is maintained, it should be measured at the center of the package top surface (encapsulant). to minimize any measurement errors, the following techniques are recommended: use 36 gauge or finer diameter k, t, or j type thermocouples. intel's laboratory testing was done using a thermocouple made by omega (part number: 5tc-ttk-36-36). attach the thermocouple bead or junction to the center of the package top surface using highly thermally conductive cements. intel's laboratory testing was done by using omega bond* (part number: ob-100). the thermocouple should b e attached at a 90 angle as shown in figure 23 . 6.1.1. tcp thermal equations for the tcp mobile pentium processor with mmx technology, an ambient temperature (t a ) is not specified directly. the only requirement is that the case temperature (t c ) is met. the ambient temperature can be calculated from the following equations: [ ] t t p t t p t t p t t p j c jc a j ja a c ca c a ja jc ca ja jc = + = - = - = + - = - q q q q q q q q ( ) where, t a and t c are ambient and case temperatures ( c) q ca = case-to-ambient thermal resistance ( c/w) q ja = junction-to-ambient thermal resistance ( c/w) q jc = junction-to-case thermal resistance ( c/w) p = maximum power consumption (watts) p (maximum power consumption) is specified in section 3.1. 6.1.2. tcp thermal characteristics the primary heat transfer path from the die of the tcp is through the back side of the die and into the pc board. there are two thermal paths traveling from the pc board to the ambient air. one is the spread of heat within the board and the dissipation of heat by the board to the ambient air. the other is the transfer of heat through the board and to the opposite side where thermal enhancements (e.g., heat sinks, pipes) are attached. solder-side heat sinking, compared to tcp component-side heat sinking, is the preferred method due to reduced risk of die damage, easier mechanical implementation and larger surface area for attachment. however, component-side heat sinking is possible. the design requirements in a component-side thermal solution are: no direct loading of inner lead bonds on the tcp, a maximum force of 4.5 kgf on the center of a clean tcp, no direct loading of the tab tape or outer lead bonds and controlled board deflection. 6.1.3. tcp pc board enhancements copper planes, thermal pads, and vias are design options that can be used to improve heat transfer from the pc board to the ambient air. tables 26 and 27 present thermal resistance data for copper plane thickness and via effects. it should be noted that although thicker copper planes will reduce the q ca of a system without any thermal enhancements, they have less effect on the q ca of a system with thermal enhancements. however, placing vias under the die will reduce the q ca of a system with and without thermal enhancements. mobile pentium ? processor with mmx? technology 65 1/9/98 11:56 am 24346802.doc intel confidential (until publication date) 255704 figure 23 . technique for measuring case temperature (t c ) on tcp table 26. tcp thermal resistance vs. copper plane thickness with and without enhancements copper plane thickness* q ca (c/watt) no enhancements q ca (c/watt) with heat pipe and al plates 1 oz. cu 18 7.8 3 oz. cu 14 7.8 note: *225 vias underneath the die table 27. tcp thermal resistance vs. thermal vias underneath the die number of vias under the die* q ca (c/watt) no enhancements 0 15 144 13 note: *3 oz. copper planes in tet boards 6.1.3.1. tcp standard test board configuration all tape carrier package (tcp) thermal measurements familiarity provided in the following tables were taken with the component soldered to a 2" x 2" test board outline. this six-layer board contains 225 vias in the die attach pad which are connected to two 3 oz. copper planes located at layers two and five. for the tcp, the vias in the die attach pad should be connected without thermal reliefs to the ground plane(s). the die is attached to the die attach pad using a thermally conductive adhesive. this test board was designed to optimize the heat spreading into the board and the heat transfer through to the opposite side of the board. note thermal resistance values should be used as guidelines only, and are highly system dependent. final system verification should always refer to the case temperature specification. mobile pentium ? processor with mmx? technology 66 1/9/98 11:56 am 24346802.doc intel confidential (until publication date) table 28. tcp thermal resistance without enhancements q jc (c/watt) q ca (c/watt) thermal resistance without enhancements 0.8 14 table 29. tcp thermal resistance with enhancements (without airflow) thermal enhancements q ca (c/w) notes heat sink 11.7 1.2" 1.2" .35" al plate 8.7 4" 4" .030" al plate with heat pipe 7.8 0.3? 1" 4" heat pipe 4?x4?x0.3? al plate table 30. tcp thermal resistance with enhancements (with airflow) thermal enhancements q ca (c/w) notes heat sink with fan @ 1.7 cfm 5.0 1.2" 1.2" .35" hs 1" 1" .4" fan heat sink with airflow @ 400 lfm 5.1 1.2?x1.2?x.35? hs heat sink with airflow @ 600 lfm 4.3 1.2" 1.2" .35" hs notes: hs = heat sink lfm = linear feet/minute cfm = cubic feet/minute united states, intel corporation 2200 mission college blvd., p.o. box 58119, santa clara, ca 95052-8119 tel: +1 408 765-8080 japan, intel japan k.k. 5-6 tokodai, tsukuba-shi, ibaraki-ken 300-26 tel: + 81-29847-8522 france, intel corporation s.a.r.l. 1, quai de grenelle, 75015 paris tel: +33 1-45717171 united kingdom, intel corporation (u.k.) ltd. pipers way, swindon, wiltshire, england sn3 1rj tel: +44 1-793-641440 germany, intel gmbh dornacher strasse 1 85622 feldkirchen/ muenchen tel: +49 89/99143-0 hong kong, intel semiconductor ltd. 32/f two pacific place, 88 queensway, central tel: +852 2844-4555 canada, intel semiconductor of canada, ltd. 190 attwell drive, suite 500 rexdale, ontario m9w 6h8 tel: +416 675-2438 |
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